Sfoglia per Relatore
Studio ed applicazione delle tecniche di Real Number Modeling e Assertion Based Verification al progetto di circuiti mixed-signal. Study and application of Real Number Modeling and Assertion Based Verification techniques to mixed-signal circuit design
2014/2015 Vallese, Pietro
Study and Design of a 32-bit High-Speed Adder
2013/2014 Stangherlin, Matteo
Study of low-noise design techniques for LDO voltage regulators
2015/2016 Oripoli, Luca
Ultra low-power SAR ADC for high resolution sensor applications, a responsive self-calibration system
2012/2013 Passamani, Antonio
Utilizzo del segnale EEG e del machine learning per la realizzazione di wearable bypass
2020/2021 FREGOLENT, MATTIA
Tipologia | Anno | Titolo | Titolo inglese | Autore | File |
---|---|---|---|---|---|
Lauree magistrali | 2014 | Studio ed applicazione delle tecniche di Real Number Modeling e Assertion Based Verification al progetto di circuiti mixed-signal. Study and application of Real Number Modeling and Assertion Based Verification techniques to mixed-signal circuit design | - | Vallese, Pietro | |
Lauree triennali | 2013 | Study and Design of a 32-bit High-Speed Adder | - | Stangherlin, Matteo | |
Lauree magistrali | 2015 | Study of low-noise design techniques for LDO voltage regulators | - | Oripoli, Luca | |
Lauree magistrali | 2012 | Ultra low-power SAR ADC for high resolution sensor applications, a responsive self-calibration system | - | Passamani, Antonio | |
Lauree triennali | 2020 | Utilizzo del segnale EEG e del machine learning per la realizzazione di wearable bypass | Use of the EEG signal and machine learning for the creation of wearable bypass | FREGOLENT, MATTIA |
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