Modeling and Transistor-level implementation of an Hybrid Low-Dropout voltage regulator in a 22nm CMOS technology

This work investigates different architectures of low-dropout (LDO) voltage regulators, considering both analog and digital approaches, with a specific emphasis on hybrid LDO solutions. In this thesis, a hybrid configuration is analyzed in which an analog LDO and a digital LDO operate in parallel. The main objective is to verify the feasibility and correct operation of this architecture, and to identify potential advantages and critical issues arising from the parallel arrangement. The proposed hybrid solution is evaluated and compared against a conventional analog LDO, with particular attention to its behavior under supply-voltage disturbances and load-current transients.