Experimental setup development for the evaluation of Gate Switching Instability in Silicon Carbide MOSFETs

Recent advances in the automotive and renewable energy industries have intensified the demand for electronic power devices capable of increasing the efficiency of energy conversion. These devices must manage high voltage levels and operate at high switching frequencies under environmental conditions characterized by significant temperature fluctuations. For these reasons, wide band gap (WBG) semiconductors are preferred over classic silicon because of their higher breakdown field, which enables the development of smaller, faster, and more efficient components. In particular, Silicon Carbide (SiC) can handle substantial power levels without compromising performance due to overheating, thanks to its high thermal conductivity. Even if SiC devices have been used since more than ten years now with promising results, the primary challenge is still ensuring consistent and reliable performance throughout the device’s entire operational cycle and extending its durability. The primary degradation factors for SiC devices are Bias Temperature Instability (BTI) and Gate Switching Instability (GSI). Both of these degradation process lead to a change in the threshold voltage of the device causing a decrease in performance during operation. However, while BTI the threshold shift vanish after a sufficient recovery time, the drift caused by GSI appear to be permanent unless high-temperature annealing or negative bias is applied. Research into the GSI mechanism is currently in its early stages; further progress depends on the ability to subject devices to stress conditions close to the real operating environments but at higher frequency to shorten the measurement time. A significant challenge in GSI characterization is the design of a testbed that combines high-frequency operation (10 MHz) with nanosecond rise/fall times while maintaining a clean, overshoot-free signal. However, these requirements are in conflicts with each others and, therefore, state-of-the-art setups are generally restricted to testing small devices with very low input capacitance; alternatively, they must limit the switching frequency, which significantly extends the required stress time. The work on which this thesis is based on, is about the development of a stress setup capable to overcome these traditional trade-offs. This will enable the testing of an extensive range of both commercial and experimental devices by reducing characterization time by an order of magnitude, providing a significant dataset that is currently unavailable. Furthermore, it will be the instrument to deepen our understanding of GSI phenomena and its correlation with the diverse architectures and materials employed in modern semiconductor manufacturing.