Advanced programming of FPGA Firmware for Real-Time Data Monitoring in the CMS Phase-2 Data Acquisition System

To handle the massive data volumes expected from the Phase-2 detector upgrade—exceeding 60 Tb/s— the Data Acquisition (DAQ) group of CMS experiment at CERN is redesigning its DAQ infrastructure. This involves deploying newly designed hardware capable of reading out sub-detector back-end boards via custom 25 Gbps optical links and streaming that data over standard TCP/IP to a commercial event-building network. The thesis work focuses on advanced FPGA firmware development for the DAQ system of this experiment, specifically working with custom electronic boards that integrate High Bandwidth Memory (HBM) chips. While this memory serves as a high-speed buffer to stream detector data to a commercial high speed network, the research investigates how to exploit the residual memory resources for advanced real-time monitoring. The goal is to implement diagnostic functions to ensure the operational integrity and reliability of the DAQ chain.