Efficiency Analysis and Optimization of Resonant Switched-Capacitor Converters in CMOS Technology

This thesis presents the design, modeling, and optimization of a fully integrated 2:1 Resonant Switched-Capacitor (ReSC) DC-DC Converter in a 130 nm CMOS technology. Thanks to the presence of a small integrated inductor into the capacitive charge-transfer path, the converter operates under Zero-Current Switching (ZCS) conditions, significantly reducing hard-switching losses and enabling high-frequency power conversion. An analytical loss model is derived to establish the optimal sizing trade-offs between flying capacitance, switch widths, and inductance. The implementation includes custom MOS switches, dynamic bulk-biasing circuits, an integrated planar spiral inductor, dedicated bootstrap drivers and CMOS buffers. Transistor-level simulations validate the theoretical framework, demonstrating high power conversion efficiency and suitability for monolithic power management applications. Finally, this work serves as a foundational framework for future developments like closed-loop output voltage regulation, on-chip clock generation, and physical layout implementation.