The rapid switching operations of power MOSFETs in modern switching-mode power supplies (SMPS) represent a major source of conducted electromagnetic interference (EMI), characterized by low-frequency fundamentals and high-frequency parasitic ringing. This thesis presents the theoretical analysis, hardware design, and experimental validation of a broadband EMI filter, specifically conceived as an educational demon- strator to investigate the critical impact of component parasitics and PCB layout on high-frequency noise suppression. The filter architecture employs a multi-stage decoupling strategy for differential mode (DM) noise mitigation, utilizing a parallel combination of electrolytic, plastic film, and ceramic capacitors. Their values were analytically selected through reverse-engineering of their equivalent series inductance (ESL) to achieve staggered self-resonant frequencies (SRF), guaranteeing a low-impedance shunt path from 10 kHz up to 20 MHz. For common mode (CM) noise suppression, a Dual-Choke topology was implemented, cascading manganese-zinc (MnZn) and nickel-zinc (NiZn) magnetic cores to ensure uninterrupted attenuation across the entire frequency spectrum. Special emphasis is placed on electromagnetic compatibility (EMC) design rules applied to the printed circuit board (PCB) layout, developed in KiCad EDA. Critical layout techniques include strictly linear signal routing to prevent crosstalk, an uninterrupted low-impedance protective earth (PE) layer, and specifically engineered copper keep-out zones beneath the magnetic components to eliminate winding-to-ground parasitic capacitance. The experimental validation was conducted utilizing a custom-engineered measurement setup, where a line impedance stabilization network (LISN) and a hardware LISN MATE were redesigned and integrated onto a single printed circuit board (PCB) to passively separate the CM and DM noise vectors. A dual-channel, dual-timebase oscilloscope configuration was adopted to simultaneously capture the macro-scale switching fundamental and the micro-scale VHF ringing without triggering instability. The experimental results confirm the broadband attenuation capabilities of the designed filter, demonstrating how a rigorous analytical selection of components, coupled with an EMC-aware PCB layout, is paramount to successfully mitigating conducted emissions.

The rapid switching operations of power MOSFETs in modern switching-mode power supplies (SMPS) represent a major source of conducted electromagnetic interference (EMI), characterized by low-frequency fundamentals and high-frequency parasitic ringing. This thesis presents the theoretical analysis, hardware design, and experimental validation of a broadband EMI filter, specifically conceived as an educational demon- strator to investigate the critical impact of component parasitics and PCB layout on high-frequency noise suppression. The filter architecture employs a multi-stage decoupling strategy for differential mode (DM) noise mitigation, utilizing a parallel combination of electrolytic, plastic film, and ceramic capacitors. Their values were analytically selected through reverse-engineering of their equivalent series inductance (ESL) to achieve staggered self-resonant frequencies (SRF), guaranteeing a low-impedance shunt path from 10 kHz up to 20 MHz. For common mode (CM) noise suppression, a Dual-Choke topology was implemented, cascading manganese-zinc (MnZn) and nickel-zinc (NiZn) magnetic cores to ensure uninterrupted attenuation across the entire frequency spectrum. Special emphasis is placed on electromagnetic compatibility (EMC) design rules applied to the printed circuit board (PCB) layout, developed in KiCad EDA. Critical layout techniques include strictly linear signal routing to prevent crosstalk, an uninterrupted low-impedance protective earth (PE) layer, and specifically engineered copper keep-out zones beneath the magnetic components to eliminate winding-to-ground parasitic capacitance. The experimental validation was conducted utilizing a custom-engineered measurement setup, where a line impedance stabilization network (LISN) and a hardware LISN MATE were redesigned and integrated onto a single printed circuit board (PCB) to passively separate the CM and DM noise vectors. A dual-channel, dual-timebase oscilloscope configuration was adopted to simultaneously capture the macro-scale switching fundamental and the micro-scale VHF ringing without triggering instability. The experimental results confirm the broadband attenuation capabilities of the designed filter, demonstrating how a rigorous analytical selection of components, coupled with an EMC-aware PCB layout, is paramount to successfully mitigating conducted emissions.

Design and Development of an EMI Filter for a Power Electronic Converter for Educational Applications

BARNABEI, LORENZO
2025/2026

Abstract

The rapid switching operations of power MOSFETs in modern switching-mode power supplies (SMPS) represent a major source of conducted electromagnetic interference (EMI), characterized by low-frequency fundamentals and high-frequency parasitic ringing. This thesis presents the theoretical analysis, hardware design, and experimental validation of a broadband EMI filter, specifically conceived as an educational demon- strator to investigate the critical impact of component parasitics and PCB layout on high-frequency noise suppression. The filter architecture employs a multi-stage decoupling strategy for differential mode (DM) noise mitigation, utilizing a parallel combination of electrolytic, plastic film, and ceramic capacitors. Their values were analytically selected through reverse-engineering of their equivalent series inductance (ESL) to achieve staggered self-resonant frequencies (SRF), guaranteeing a low-impedance shunt path from 10 kHz up to 20 MHz. For common mode (CM) noise suppression, a Dual-Choke topology was implemented, cascading manganese-zinc (MnZn) and nickel-zinc (NiZn) magnetic cores to ensure uninterrupted attenuation across the entire frequency spectrum. Special emphasis is placed on electromagnetic compatibility (EMC) design rules applied to the printed circuit board (PCB) layout, developed in KiCad EDA. Critical layout techniques include strictly linear signal routing to prevent crosstalk, an uninterrupted low-impedance protective earth (PE) layer, and specifically engineered copper keep-out zones beneath the magnetic components to eliminate winding-to-ground parasitic capacitance. The experimental validation was conducted utilizing a custom-engineered measurement setup, where a line impedance stabilization network (LISN) and a hardware LISN MATE were redesigned and integrated onto a single printed circuit board (PCB) to passively separate the CM and DM noise vectors. A dual-channel, dual-timebase oscilloscope configuration was adopted to simultaneously capture the macro-scale switching fundamental and the micro-scale VHF ringing without triggering instability. The experimental results confirm the broadband attenuation capabilities of the designed filter, demonstrating how a rigorous analytical selection of components, coupled with an EMC-aware PCB layout, is paramount to successfully mitigating conducted emissions.
2025
Design and Development of an EMI Filter for a Power Electronic Converter for Educational Applications
The rapid switching operations of power MOSFETs in modern switching-mode power supplies (SMPS) represent a major source of conducted electromagnetic interference (EMI), characterized by low-frequency fundamentals and high-frequency parasitic ringing. This thesis presents the theoretical analysis, hardware design, and experimental validation of a broadband EMI filter, specifically conceived as an educational demon- strator to investigate the critical impact of component parasitics and PCB layout on high-frequency noise suppression. The filter architecture employs a multi-stage decoupling strategy for differential mode (DM) noise mitigation, utilizing a parallel combination of electrolytic, plastic film, and ceramic capacitors. Their values were analytically selected through reverse-engineering of their equivalent series inductance (ESL) to achieve staggered self-resonant frequencies (SRF), guaranteeing a low-impedance shunt path from 10 kHz up to 20 MHz. For common mode (CM) noise suppression, a Dual-Choke topology was implemented, cascading manganese-zinc (MnZn) and nickel-zinc (NiZn) magnetic cores to ensure uninterrupted attenuation across the entire frequency spectrum. Special emphasis is placed on electromagnetic compatibility (EMC) design rules applied to the printed circuit board (PCB) layout, developed in KiCad EDA. Critical layout techniques include strictly linear signal routing to prevent crosstalk, an uninterrupted low-impedance protective earth (PE) layer, and specifically engineered copper keep-out zones beneath the magnetic components to eliminate winding-to-ground parasitic capacitance. The experimental validation was conducted utilizing a custom-engineered measurement setup, where a line impedance stabilization network (LISN) and a hardware LISN MATE were redesigned and integrated onto a single printed circuit board (PCB) to passively separate the CM and DM noise vectors. A dual-channel, dual-timebase oscilloscope configuration was adopted to simultaneously capture the macro-scale switching fundamental and the micro-scale VHF ringing without triggering instability. The experimental results confirm the broadband attenuation capabilities of the designed filter, demonstrating how a rigorous analytical selection of components, coupled with an EMC-aware PCB layout, is paramount to successfully mitigating conducted emissions.
EMI
Filter
Power Electronics
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.12608/116571