Architectures such as Samsung’s function-in-memory DRAM (FIMDRAM), which place computation near high-bandwidth memory (HBM), expose target-specific instruction, address, register, resource, and host-control semantics. Exploring architectural alternatives requires compiler support that preserves common program representations while isolating the decisions that change with the target. This thesis extends the Multi-Level Intermediate Representation (MLIR)-based Cinnamon infrastructure with a modular FIMDRAM backend for generating, checking, and comparing candidate configurations. The implementation introduces a FIMDRAM dialect, a selected-program representation, declarative target descriptions, exchangeable policies, pipeline recipes, and cumulative verification contracts. Samsung’s original FIMDRAM address-aligned mode (AAM) design and Kukić’s modified host-driven variant, called host-driven FIMDRAM (HD-FIMDRAM) in this thesis, serve as source-backed case studies. Both profiles share the representation and lowering flow while specializing instruction selection, physical addressing, register allocation, placement, binary encoding, and host-command generation. The evaluation covers six arithmetic workload families across five experiment groups. All 36 primary configurations compile successfully and pass the source-work and model-consistency checks. Replacing the register allocator preserves the eight checked aggregate counts while allowing physical register assignments to differ. Replacing the memory transaction mapping produces 32 successful compilations and four diagnosed rejections, demonstrating how AAM layout affects replay grouping and register legality within the same pipeline. Capacity sweeps show automatic partitioning of independent vector work and identify per-launch limits for reductions that the backend does not yet decompose. Separate matrix-multiplication experiments use generator-defined output tiles and show that tile shape can change both program size and address-derived register compatibility. These results demonstrate a modular backend within Cinnamon for generating and comparing FIMDRAM configurations. Compiler policies can change within a shared lowering structure while their effects on generated artifacts and compilation legality remain explicit. The evaluation establishes these properties through static artifacts rather than measured runtime performance. The resulting programs and host-command descriptions provide a basis for future automated search, functional validation, and timing simulation.
Architectures such as Samsung’s function-in-memory DRAM (FIMDRAM), which place computation near high-bandwidth memory (HBM), expose target-specific instruction, address, register, resource, and host-control semantics. Exploring architectural alternatives requires compiler support that preserves common program representations while isolating the decisions that change with the target. This thesis extends the Multi-Level Intermediate Representation (MLIR)-based Cinnamon infrastructure with a modular FIMDRAM backend for generating, checking, and comparing candidate configurations. The implementation introduces a FIMDRAM dialect, a selected-program representation, declarative target descriptions, exchangeable policies, pipeline recipes, and cumulative verification contracts. Samsung’s original FIMDRAM address-aligned mode (AAM) design and Kukić’s modified host-driven variant, called host-driven FIMDRAM (HD-FIMDRAM) in this thesis, serve as source-backed case studies. Both profiles share the representation and lowering flow while specializing instruction selection, physical addressing, register allocation, placement, binary encoding, and host-command generation. The evaluation covers six arithmetic workload families across five experiment groups. All 36 primary configurations compile successfully and pass the source-work and model-consistency checks. Replacing the register allocator preserves the eight checked aggregate counts while allowing physical register assignments to differ. Replacing the memory transaction mapping produces 32 successful compilations and four diagnosed rejections, demonstrating how AAM layout affects replay grouping and register legality within the same pipeline. Capacity sweeps show automatic partitioning of independent vector work and identify per-launch limits for reductions that the backend does not yet decompose. Separate matrix-multiplication experiments use generator-defined output tiles and show that tile shape can change both program size and address-derived register compatibility. These results demonstrate a modular backend within Cinnamon for generating and comparing FIMDRAM configurations. Compiler policies can change within a shared lowering structure while their effects on generated artifacts and compilation legality remain explicit. The evaluation establishes these properties through static artifacts rather than measured runtime performance. The resulting programs and host-command descriptions provide a basis for future automated search, functional validation, and timing simulation.
Modular Compiler Design for Emerging Compute-near-HBM Architectures
BOTTARI, ALBERTO
2025/2026
Abstract
Architectures such as Samsung’s function-in-memory DRAM (FIMDRAM), which place computation near high-bandwidth memory (HBM), expose target-specific instruction, address, register, resource, and host-control semantics. Exploring architectural alternatives requires compiler support that preserves common program representations while isolating the decisions that change with the target. This thesis extends the Multi-Level Intermediate Representation (MLIR)-based Cinnamon infrastructure with a modular FIMDRAM backend for generating, checking, and comparing candidate configurations. The implementation introduces a FIMDRAM dialect, a selected-program representation, declarative target descriptions, exchangeable policies, pipeline recipes, and cumulative verification contracts. Samsung’s original FIMDRAM address-aligned mode (AAM) design and Kukić’s modified host-driven variant, called host-driven FIMDRAM (HD-FIMDRAM) in this thesis, serve as source-backed case studies. Both profiles share the representation and lowering flow while specializing instruction selection, physical addressing, register allocation, placement, binary encoding, and host-command generation. The evaluation covers six arithmetic workload families across five experiment groups. All 36 primary configurations compile successfully and pass the source-work and model-consistency checks. Replacing the register allocator preserves the eight checked aggregate counts while allowing physical register assignments to differ. Replacing the memory transaction mapping produces 32 successful compilations and four diagnosed rejections, demonstrating how AAM layout affects replay grouping and register legality within the same pipeline. Capacity sweeps show automatic partitioning of independent vector work and identify per-launch limits for reductions that the backend does not yet decompose. Separate matrix-multiplication experiments use generator-defined output tiles and show that tile shape can change both program size and address-derived register compatibility. These results demonstrate a modular backend within Cinnamon for generating and comparing FIMDRAM configurations. Compiler policies can change within a shared lowering structure while their effects on generated artifacts and compilation legality remain explicit. The evaluation establishes these properties through static artifacts rather than measured runtime performance. The resulting programs and host-command descriptions provide a basis for future automated search, functional validation, and timing simulation.| File | Dimensione | Formato | |
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https://hdl.handle.net/20.500.12608/117690