The topic of this thesis is the study and the development of methodologies for the automation of the design procedure, both schematic and layout, targeting analog circuits. The target is the analog portion of a chip because, even if sometimes it is not the dominant one in terms of area occupation, it is subject to a more difficult automation approach due to the required analog characteristics. In particular, the work of this thesis focuses on the driver for a boost dc-dc converter. The reasons behind this study are different, starting with the challenge of automating the analog design process and ending up with responding to the growing demand in the market. There is in all effects a change in the methodology, i.e. the challenge is to obtain a generator of instances which are adaptable and flexible. Tools have been developed internally at Infineon to achieve this goal and they have been used in this project to implement a complete workflow. In Chap.1 a brief introduction to the work is presented, along with descriptions of the tools used. In Chap.2 the first part of the workflow is treated: the schematic generator; a detailed presentation of the Driver follows, with its characterization and design theory. In Chap.3 the second part of the workflow is presented: the layout generator. Finally in Chap.4 results are presented with the necessary verification.
The topic of this thesis is the study and the development of methodologies for the automation of the design procedure, both schematic and layout, targeting analog circuits. The target is the analog portion of a chip because, even if sometimes it is not the dominant one in terms of area occupation, it is subject to a more difficult automation approach due to the required analog characteristics. In particular, the work of this thesis focuses on the driver for a boost dc-dc converter. The reasons behind this study are different, starting with the challenge of automating the analog design process and ending up with responding to the growing demand in the market. There is in all effects a change in the methodology, i.e. the challenge is to obtain a generator of instances which are adaptable and flexible. Tools have been developed internally at Infineon to achieve this goal and they have been used in this project to implement a complete workflow. In Chap.1 a brief introduction to the work is presented, along with descriptions of the tools used. In Chap.2 the first part of the workflow is treated: the schematic generator; a detailed presentation of the Driver follows, with its characterization and design theory. In Chap.3 the second part of the workflow is presented: the layout generator. Finally in Chap.4 results are presented with the necessary verification.
Analog generator for a driver of a boost dc-dc converter
DEMIRI, DAVID
2021/2022
Abstract
The topic of this thesis is the study and the development of methodologies for the automation of the design procedure, both schematic and layout, targeting analog circuits. The target is the analog portion of a chip because, even if sometimes it is not the dominant one in terms of area occupation, it is subject to a more difficult automation approach due to the required analog characteristics. In particular, the work of this thesis focuses on the driver for a boost dc-dc converter. The reasons behind this study are different, starting with the challenge of automating the analog design process and ending up with responding to the growing demand in the market. There is in all effects a change in the methodology, i.e. the challenge is to obtain a generator of instances which are adaptable and flexible. Tools have been developed internally at Infineon to achieve this goal and they have been used in this project to implement a complete workflow. In Chap.1 a brief introduction to the work is presented, along with descriptions of the tools used. In Chap.2 the first part of the workflow is treated: the schematic generator; a detailed presentation of the Driver follows, with its characterization and design theory. In Chap.3 the second part of the workflow is presented: the layout generator. Finally in Chap.4 results are presented with the necessary verification.File | Dimensione | Formato | |
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https://hdl.handle.net/20.500.12608/39197