Some systems are easier to prototype than others. That's an indisputable fact in the world of integrated circuit design. This work explores and develops a novel approach to a virtual platform for verification environment and lab test acceleration, by means of a LabVIEW-FPGA system. The first part goes through the process of porting the project to an FPGA, which is a well known concept but nonetheless makes up a very important part of the project, due to the differences between ASIC and FPGA systems. Along the same lines, there's also the design of two application-specific blocks: The 'LDO handler' and 'Monitoring' blocks, which play signaling roles in the digital system, with the 'LDO handler' managing the operation of emulated and/or real LDOs, and the 'monitoring' block checking the operation of said systems to ensure that they're always operating in safe conditions. For real systems there's not much mystery: an equivalent analog model is created from discrete components and connected to the GPIO, but for emulated systems there needs to be a way to create this interface between the real digital system running in an FPGA, and the emulated system running on a host computer. This process will also be explored, showing how this can be done and discussing some of the design considerations of such a system. Lastly it all comes together, with the system finally being fully integrated with the various components created along the way and is ready to perform the tests. By the end of this work, we'll have a proof of concept capable of demonstrating the viability of the virtual platform testing approach on bigger and more complex systems.

Some systems are easier to prototype than others. That's an indisputable fact in the world of integrated circuit design. This work explores and develops a novel approach to a virtual platform for verification environment and lab test acceleration, by means of a LabVIEW-FPGA system. The first part goes through the process of porting the project to an FPGA, which is a well known concept but nonetheless makes up a very important part of the project, due to the differences between ASIC and FPGA systems. Along the same lines, there's also the design of two application-specific blocks: The 'LDO handler' and 'Monitoring' blocks, which play signaling roles in the digital system, with the 'LDO handler' managing the operation of emulated and/or real LDOs, and the 'monitoring' block checking the operation of said systems to ensure that they're always operating in safe conditions. For real systems there's not much mystery: an equivalent analog model is created from discrete components and connected to the GPIO, but for emulated systems there needs to be a way to create this interface between the real digital system running in an FPGA, and the emulated system running on a host computer. This process will also be explored, showing how this can be done and discussing some of the design considerations of such a system. Lastly it all comes together, with the system finally being fully integrated with the various components created along the way and is ready to perform the tests. By the end of this work, we'll have a proof of concept capable of demonstrating the viability of the virtual platform testing approach on bigger and more complex systems.

FPGA-LabVIEW Virtual Platform for Verification Environment and Lab Test Acceleration

FASOLATO BASILIO, ELDER
2022/2023

Abstract

Some systems are easier to prototype than others. That's an indisputable fact in the world of integrated circuit design. This work explores and develops a novel approach to a virtual platform for verification environment and lab test acceleration, by means of a LabVIEW-FPGA system. The first part goes through the process of porting the project to an FPGA, which is a well known concept but nonetheless makes up a very important part of the project, due to the differences between ASIC and FPGA systems. Along the same lines, there's also the design of two application-specific blocks: The 'LDO handler' and 'Monitoring' blocks, which play signaling roles in the digital system, with the 'LDO handler' managing the operation of emulated and/or real LDOs, and the 'monitoring' block checking the operation of said systems to ensure that they're always operating in safe conditions. For real systems there's not much mystery: an equivalent analog model is created from discrete components and connected to the GPIO, but for emulated systems there needs to be a way to create this interface between the real digital system running in an FPGA, and the emulated system running on a host computer. This process will also be explored, showing how this can be done and discussing some of the design considerations of such a system. Lastly it all comes together, with the system finally being fully integrated with the various components created along the way and is ready to perform the tests. By the end of this work, we'll have a proof of concept capable of demonstrating the viability of the virtual platform testing approach on bigger and more complex systems.
2022
FPGA-LabVIEW Virtual Platform for Verification Environment and Lab Test Acceleration
Some systems are easier to prototype than others. That's an indisputable fact in the world of integrated circuit design. This work explores and develops a novel approach to a virtual platform for verification environment and lab test acceleration, by means of a LabVIEW-FPGA system. The first part goes through the process of porting the project to an FPGA, which is a well known concept but nonetheless makes up a very important part of the project, due to the differences between ASIC and FPGA systems. Along the same lines, there's also the design of two application-specific blocks: The 'LDO handler' and 'Monitoring' blocks, which play signaling roles in the digital system, with the 'LDO handler' managing the operation of emulated and/or real LDOs, and the 'monitoring' block checking the operation of said systems to ensure that they're always operating in safe conditions. For real systems there's not much mystery: an equivalent analog model is created from discrete components and connected to the GPIO, but for emulated systems there needs to be a way to create this interface between the real digital system running in an FPGA, and the emulated system running on a host computer. This process will also be explored, showing how this can be done and discussing some of the design considerations of such a system. Lastly it all comes together, with the system finally being fully integrated with the various components created along the way and is ready to perform the tests. By the end of this work, we'll have a proof of concept capable of demonstrating the viability of the virtual platform testing approach on bigger and more complex systems.
FPGA
Verification
Lab Test
LabVIEW
Virtual Platform
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.12608/45804