Exploring the Potential of Metal-Oxide Based Logic Gates for Digital Adder Circuits

Printed electronics (PE) have attracted tremendous attention to enable the design space exploration for electronic applications. Due to additive manufacturing and compatibility with a variety of substrates, large scale integrated circuits with low cost margins can be attained. To reach fundamental digital building blocks used for arithmetical operations, the objectives for this research covers two major themes in the domain of flexible and printed electronics. Firstly, the fabrication of electrolyte-gated field-effect transistors (EGFETs) will be discussed. A proper material stack with optimized characteristics is a crucial step to fabricate digital circuits. Therefore, the properties of the EGFETs need to be carefully chosen to met the requirements of the analyzed circuits, in form of logic gates and adders. Not only the properties of the EGFETs will be considered but also different circuit topology are evaluated to improve the performance and reduce the transistor count of logic gates. Thereby, state-of-the-art logic gate as well as pass logic designs, comprising EGFETs and resistors, are evaluated. To achieve the desired circuit functionality, it is crucial that the EGFETs only turn-on at positive gate-source voltages. Therefore, it is important that the threshold voltage of the EGFETs are within a certain voltage range (100 mV – 200 mV). To ensure that the threshold voltage of the EGFETs are within the desired voltage range, the curing conditions of the precursor based indium oxide semiconductor film is evaluated. In this regard, the annealing temperature is assessed to be 300 °C due to the fact that during the crystallization of the film oxygen vacancies will introduced into the system and by reducing the temperature the conductivity as a result will reduce which leads to a mean value of the threshold voltage to set at 0.1V . This EGFETs are then used to print logic gates. The inverter showed in maximum gain of 7 at supply voltage of VDD=1 V and propagation delay time of 3.2 ms. These values demonstrate that the EGFETs are feasible to design more complex circuits, such as adders. Besides inverters, NAND, NOR, and XOR gates are evaluated. Subsequently, it is demonstrated that the transistor count can be reduced by approximately 50%, when pass logic gate designs are chosen over conventional designs.