Design of a D-Band Power Amplifier for Radar Applications in 28nm CMOS Technology

Radar applications require both digital and analog circuits in their signal path. CMOS technology proved to be the best solution for implementing digital processing circuits, with its superior efficiency compared to other bipolar based technology. Commonly, the RF part of the chain can be implemented using an HBT technology thanks to its high speed, high gain and high linearity properties. However, since the digital part is designed using CMOS technology, integrating the two technologies can become cumbersome, both for technical and logistical reasons. The purpose of this thesis is to understand which levels of performance are obtainable if the RF part is designed using solely CMOS technology. This work makes use of TSMC 28 nm CMOS technology to implement the power amplifier in the radar chain. The main challenge is operating at a high frequency of 120 GHz, which pushes the devices close to their transit frequency limit and heavily restricts the gain. The objective of the overall power amplifier chain is to reach an output power between 5 and 10 dBm and a power gain equal to 15 dB. This work is focused only in the design of the last stage of the chain, which determines the output power capability of the entire system and sets the standard regarding the gain of the previous stages. The thesis is divided into three sections: the first one is dedicated to theoretical analysis regarding radar systems and power amplifiers. The second one starts from an analysis of the technology in use, highlighting the main figures of merit of a CMOS transistor. Then it proceeds presenting the design of a common source power amplifier starting from the schematic level and concluding with the layout. Finally the last section proposes a different power amplifier topology which is the cascode configuration, analysed both in the schematic and layout level. The thesis closes with the analysis of the difference in performance between the two designs.