A Comparative Study of Class-B and Class-F LC DCOs in 28 nm CMOS for High-Performance PLLs

In recent years, the automotive field has seen radar systems become a key enabler of Advanced Driver-Assistance Systems (ADAS), requiring stringent phase noise performance to guarantee accurate and reliable object detection. The Digital Phase-Locked Loop (DPLL) is a critical component responsible for synthesizing the mm-wave frequencies required for high resolution, and it contains a crucial element: the digital controlled oscillator (DCO). The DCO is a circuit that translates its input control word into a sinusoidal output voltage, and its performance has a significant impact on the system’s accuracy, as it is the primary contributor to phase noise. To cope with mm-wave DCO bad phase noise and limited tuning range due to low capacitor quality factors and high parasitics impact, the frequency synthesizer is composed by a low frequency DPLL together with frequency multipliers, which multiply the DPLL frequency by a factor of N. In this context, the class-F oscillator appears particularly well-suited, as it is capable of generating a third harmonic voltage, which inherently provides a frequency multiplication factor of 3, thereby enabling a reduction in area consumption. This thesis investigates the design of a class-F DCO and compares its performance to that of a class-B oscillator, which serves as a benchmark circuit and it is divided into two main parts. The first part presents a theoretical analysis of the two topologies, with a special emphasis on phase noise reduction techniques that can be potentially applied to both circuits. The second part focuses on the actual design of the DCOs, with a particular focus on the layout of the magnetic elements. Finally, the performances of the class-B and class-F DCOs are compared and evaluated.