Gate Switching Instability in SiC power MOSFETs

In the current context, wide-bandgap semiconductors are receiving increasing attention for their potential in renewable energy applications and power conversion efficiency. Specifically, Silicon Carbide (SiC) has recently been adopted for the development of high-density power devices, which are widely used in industrial and automotive sectors. As a result, Si-based technology is gradually being replaced by SiC technology, primarily due to its exceptional properties, such as low-loss switching capability and a high electric field, which enable more efficient and compact energy conversion systems. However, recent studies have identified a new degradation mechanism affecting SiC MOSFETs when they are switched in bipolar mode for prolonged time. This phenomenon, known as Gate Switching Instability (GSI), leads to degradation beyond that caused by the well-established Bias Temperature Instability (BTI), resulting in a greater threshold voltage drift in the stressed device. In order to simulate a real-lifetime operation of a SiC MOSFET, long-time Gate Switching Stress (GSS) measurements are conducted on the devices. A measurement setup and procedure have been specifically developed to investigate Gate Switching Instability phenomenon in SiC MOSFETs while avoiding some typical problems encountered in literature. A very high switching frequency of up to 5 MHz is employed to minimize the contribution from constant voltage stress. Additionally, the devices under test are sampled directly on-wafer, enhancing both reproducibility and automation. Rather than using large packaged application-like devices, small test structures are measured, which helps avoid self-heating effects due to the excellent thermal conductivity of the wafer. Furthermore, an aggressive preconditioning procedure has been introduced to prevent interference with slow interface traps that are responsible for hysteresis in transfer curves and to focus primarily on the contribution of quasi-permanent traps formed during the switching cycles. In addition, a fully tunable three-level voltage waveform is used as the stress waveform in GSS tests and Charge Pumping (CP) measurements to further investigate the interface behavior. This innovative method has enabled a focused investigation of the SiO2/SiC interface, specifically targeting the mechanisms responsible for Gate Switching Instability. As a result, a new phenomenon termed “early-GSI”, not previously recognized in literature, has been identified, providing a clear distinction between GSI and BTI even at low switching cycle counts. Moreover, the CP results matched the results from GSS, supporting the assumption that interface recombination drives GSI and establishing a foundation for using CP as a predictor for GSS. The work was carried out entirely in the laboratories of the Department of Advanced Technologies and Micro systems at the Robert Bosch GmbH Research Campus in Renningen, Stuttgart, Germany.