The purpose of this internship thesis is to develop and test a transceiver for interconnecting PCBs. The goal is to create a high-speed differential transmission circuit utilizing a single pair of wires within a standard copper cable. This will present several design challenges that require the development of a discrete component transceiver, along with its data encoding scheme. The project will also involve the development of FPGA code to encode, transmit, receive, and decode the data stream. Since the project will be utilizing uncommon encoding schemes, the FPGA will act as a peripheral capable of generating the necessary signals for the transceiver. Once the signals for communication have been determined, this thesis will focus on the development and testing of several topologies. During the internship, many ideas were considered, although most did not provide viable solutions. Only the most relevant ideas are presented in this thesis, where the realization of four prototypes is discussed. Two prototypes will be dedicated to exploring and analyzing the designed topologies, while the other two will focus on finalizing the most effective ones.

The purpose of this internship thesis is to develop and test a transceiver for interconnecting PCBs. The goal is to create a high-speed differential transmission circuit utilizing a single pair of wires within a standard copper cable. This will present several design challenges that require the development of a discrete component transceiver, along with its data encoding scheme. The project will also involve the development of FPGA code to encode, transmit, receive, and decode the data stream. Since the project will be utilizing uncommon encoding schemes, the FPGA will act as a peripheral capable of generating the necessary signals for the transceiver. Once the signals for communication have been determined, this thesis will focus on the development and testing of several topologies. During the internship, many ideas were considered, although most did not provide viable solutions. Only the most relevant ideas are presented in this thesis, where the realization of four prototypes is discussed. Two prototypes will be dedicated to exploring and analyzing the designed topologies, while the other two will focus on finalizing the most effective ones.

Developement of high speed differential data transceiver for Horeca appliances

PALLARO, ALESSANDRO
2024/2025

Abstract

The purpose of this internship thesis is to develop and test a transceiver for interconnecting PCBs. The goal is to create a high-speed differential transmission circuit utilizing a single pair of wires within a standard copper cable. This will present several design challenges that require the development of a discrete component transceiver, along with its data encoding scheme. The project will also involve the development of FPGA code to encode, transmit, receive, and decode the data stream. Since the project will be utilizing uncommon encoding schemes, the FPGA will act as a peripheral capable of generating the necessary signals for the transceiver. Once the signals for communication have been determined, this thesis will focus on the development and testing of several topologies. During the internship, many ideas were considered, although most did not provide viable solutions. Only the most relevant ideas are presented in this thesis, where the realization of four prototypes is discussed. Two prototypes will be dedicated to exploring and analyzing the designed topologies, while the other two will focus on finalizing the most effective ones.
2024
Developement of high speed differential data transceiver for Horeca appliances
The purpose of this internship thesis is to develop and test a transceiver for interconnecting PCBs. The goal is to create a high-speed differential transmission circuit utilizing a single pair of wires within a standard copper cable. This will present several design challenges that require the development of a discrete component transceiver, along with its data encoding scheme. The project will also involve the development of FPGA code to encode, transmit, receive, and decode the data stream. Since the project will be utilizing uncommon encoding schemes, the FPGA will act as a peripheral capable of generating the necessary signals for the transceiver. Once the signals for communication have been determined, this thesis will focus on the development and testing of several topologies. During the internship, many ideas were considered, although most did not provide viable solutions. Only the most relevant ideas are presented in this thesis, where the realization of four prototypes is discussed. Two prototypes will be dedicated to exploring and analyzing the designed topologies, while the other two will focus on finalizing the most effective ones.
Transceiver
Data
Transmission
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.12608/84258