Design of 32-Bit Floating Point CORDIC Co-Processor

This thesis centers on the design of a CORDIC co-processor tailored for the 32-bit floating-point data format, specifically to compute sine and cosine values. The co-processor complies with the IEEE-754 standard for single-precision floating-point numbers and employs the CORDIC algorithm, which necessitates multiple additions and multiplications per iteration. A specialized floating-point adder has been created to implement the CORDIC algorithm, and a binary subtractor has been used for the multiplication operation. Various floating-point adder architectures have been evaluated to identify the most optimized structure. The final proposal includes pipelined and serial architectures, synthesized for 130nm (UMC) and 22nm (Global Foundry) technology nodes. The co-processor core is modeled in VHDL, providing a robust solution for efficient computation.