The evolution of high-performance processors and artificial intelligence accelerators imposes extremely stringent requirements on voltage regulation modules (VRMs), which are characterized by low output voltages, high currents, and fast load transients. In this context, this thesis develops and validates a digital autotuning technique for multiphase VRM control, with the goal of ensuring stability and dynamic performance even in the presence of component variations and lifetime degradation. After reviewing the main autotuning strategies, a hardware-efficient approach based on sinusoidal injection is selected. This method estimates the bandwidth and phase margin of the VRM, enabling realtime adaptation of the PID controller coefficients. The algorithm was simulated using fixed-point arithmetic models to analyze quantization effects, and subsequently implemented in VHDL on FPGA. Experimental results demonstrate the system’s ability to maintain the desired phase margin and bandwidth, ensuring accurate voltage regulation under step loads up to hundreds of amperes. This work highlights how digital autotuning can represent an effective and scalable solution for future power delivery systems of high-performance AI processors.

Development of Digital Controller Tuning for Voltage Regulation Modules of AI processors

DE DAVIDE, ALBERTO
2024/2025

Abstract

The evolution of high-performance processors and artificial intelligence accelerators imposes extremely stringent requirements on voltage regulation modules (VRMs), which are characterized by low output voltages, high currents, and fast load transients. In this context, this thesis develops and validates a digital autotuning technique for multiphase VRM control, with the goal of ensuring stability and dynamic performance even in the presence of component variations and lifetime degradation. After reviewing the main autotuning strategies, a hardware-efficient approach based on sinusoidal injection is selected. This method estimates the bandwidth and phase margin of the VRM, enabling realtime adaptation of the PID controller coefficients. The algorithm was simulated using fixed-point arithmetic models to analyze quantization effects, and subsequently implemented in VHDL on FPGA. Experimental results demonstrate the system’s ability to maintain the desired phase margin and bandwidth, ensuring accurate voltage regulation under step loads up to hundreds of amperes. This work highlights how digital autotuning can represent an effective and scalable solution for future power delivery systems of high-performance AI processors.
2024
Development of Digital Controller Tuning for Voltage Regulation Modules of AI processors
Digital control
Autotuning
FPGA implementation
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.12608/90357