Design Automation for High-Efficiency Stacked Integrated DC-DC Converters

The stacking of low voltage transistors brings several advantages for the design of power management integrated circuits (PMICs). Process nodes and, thereby, the I/O voltage of the core devices shrink down, while the supply voltages of many applications cannot be reduced at the same rate. The stacking of low-voltage devices is often more area- and energy-efficient compared with using one high voltage transistor. Up to now, on the literature is not present a unified model which describes the behavior of two stacked transistors during the turn-on and turn-off transients, and able to estimate the switching losses. Consequently, when it comes the time for an electronic engineer to design a DC-DC converter with stacked topology, is always though to find a good point of start in terms of devices parameters. This leads to the idea at the base of this work: to develop a model able to give an estimation of the total efficiency for a two-stacked buck converter in function of many parameters, like transistors channel´s length and width, switching frequency, output current, supply voltage, and so on. The buck model has been implemented through python code and uses interpolated data from look-up tables (LUT), provided by the company and related to the case-of-study technology. In order to validate the model, a statistical analysis has been carried out, comparing model results with several different input sets, with the results of simulations in a SPICE based environment. In the future the model can be expanded including new input parameters, like the bulk connection of the cascaded transistors.