Agentic AI Workflow for Digital Functional Verification Components Generation

The increasing complexity of digital circuit design poses significant challenges across all stages of the development process, particularly during pre-silicon functional verification, in terms of time and resources. Among the key components of the verification process, we have functional coverage, which plays a critical role in evaluating verification completeness and requires a substantial investment of manual effort and expertise. This thesis explores the potential of generative AI, specifically Large Language Models (LLMs), to assist in automating and accelerating the generation of functional coverage models. In this context, an agentic AI workflow has been developed to investigate how LLMs can interpret project requirements written in natural language and generate structured functional coverage components in SystemVerilog. The objective is to evaluate whether generative AI can reduce the overall digital pre-silicon verification effort, thereby accelerating time-to-market.