In this work is reported the characterization of the threshold voltage instability in vertical GaN trench MOSFETs with three different types of oxide deposition with a constant gate oxide thickness of 70 nm: (a) pure Low Pressure Chemical Vapor Deposition (LPCVD), (b) 5 nm of Atomic Layer Deposition (ALD) and 65 nm of LPCVD and (c) 15 nm of ALD and 55 nm of LPCVD. The experimental analysis is based on fast threshold-voltage transient analysis and fast capacitance-voltage characteristics in order to analyse the charge trapping effects on the device performances. The results shows that the minimum charge trapping is obtained on the devices (b) with 5 nm of ALD dielectric; this behaviour is ascribed to the presence of defects between the ALD and LPCVD layers, that results in a sheet of negative charge that decreases the electric field at the oxide-semiconductor region, thus minimizing charge trapping. The model was validated by means of TCAD simulations that confirmed the previous hypothesis.
In questa tesi si andrà a caratterizzare l’instabilità della tensione di soglia in transistor verticali in GaN con tre diverse deposizioni dell’ossido con uno spessore di 70 nm: (a) solamente Low Pressure Chemical Vapor Deposition (LPCVD), (b) 5 nm di Atomic Layer Deposition (ALD) e 65 nm di LPCVD e (c) 15 nm di ALD e 55 nm di LPCVD. I dispositivi sono analizzati con diverse tipologie di misura, per esempio VTH transient e fast CV in modo da analizzare gli effetti che l’intrappolamento ha sulle performance del dispositivo. I risultati delle misure mostrano che la minima variazione nella carica intrappolata si ha per i dispositivi (b) che hanno 5 nm di ALD; questo comportamento è dovuto alla presenza di stati interfaccia tra l’ossido depositato tramite ALD e quello depositato tramite LPCVD. Questo risulta in una concentrazione di carica negativa che diminuisce l’intensità del campo elettrico nella regione tra ossido e semiconduttore, riducendo l’intrappolamento di carica. Nella seconda parte di questo elaborato andremo a modellizzare il comportamento dello shift di soglia tramite software TCAD.
Combined experimental and simulation analysis of VTH instability in vertical GaN Trench MOSFETs
CAZZADORE, ANNA
2024/2025
Abstract
In this work is reported the characterization of the threshold voltage instability in vertical GaN trench MOSFETs with three different types of oxide deposition with a constant gate oxide thickness of 70 nm: (a) pure Low Pressure Chemical Vapor Deposition (LPCVD), (b) 5 nm of Atomic Layer Deposition (ALD) and 65 nm of LPCVD and (c) 15 nm of ALD and 55 nm of LPCVD. The experimental analysis is based on fast threshold-voltage transient analysis and fast capacitance-voltage characteristics in order to analyse the charge trapping effects on the device performances. The results shows that the minimum charge trapping is obtained on the devices (b) with 5 nm of ALD dielectric; this behaviour is ascribed to the presence of defects between the ALD and LPCVD layers, that results in a sheet of negative charge that decreases the electric field at the oxide-semiconductor region, thus minimizing charge trapping. The model was validated by means of TCAD simulations that confirmed the previous hypothesis.| File | Dimensione | Formato | |
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https://hdl.handle.net/20.500.12608/94119