Screening procedure optimization for flash memory retention during production testing

Nowadays, flash memories are expected to meet stringent data retention constraints as required by standards, in order to ensure the reliability of devices throughout their entire customer lifetime. Memories must be properly tested during the production phases in order to screen all and only the devices which would not fulfill the retention specifications. To achieve them, accelerated retention tests are conducted at high temperatures. These tests aim to simulate the conditions experienced over the entire customer life of the device within a few hours. However, there are instances where the applied temperature stress is not able to replicate the entire mission profile. In such cases, a safety margin, known as a guardband, must be applied during the reading operation to compensate for this bake lack. In this thesis, it has been examined both program memory (PMEM) and data memory (DMEM) embedded in a specific Infineon’s automotive microcontroller. The goal of this study is to investigate the bake contribution on the overall guardband, used on PMEM or DMEM cell read operations in the production test. In the first part of the thesis, the voltage shift loss of the read window in a programmed memory, was extracted from the retention test results of the production. It is fundamental to highlight that only the contribution of the bake effect has been isolated and considered in this analysis. Subsequently, in the second part, another analysis was conducted to predict the voltage shift loss at the end of the customer's life. The prediction was carried out by using accelerated tests performed during qualification process and employing the Arrhenius model. To conclude the analysis, the two voltage shifts were compared to determine whether the application of a voltage guardband is necessary for this device. The voltage results were finally translated into current values in order to compare them with the actual settings used by the test program, which defines guardbands on the current domain. Since the bake test is conducted at the wafer level, it is not possible to customize the guardband specifically for each customer. The guardband definition is therefore derived by the worst-case mission profile, thus accomplishing the most demanding customer. As a final remark, it is important to emphasize that the outcomes of this thesis are highly influenced by the device technology of the analyzed product.